1. Technical Field
The present invention relates to a method of manufacturing a semiconductor device and a semiconductor device.
2. Related Art
In recent years, with a reduction in the size of LSIs, a driving current has deteriorated due to the depletion of a polysilicon gate electrode of each metal-oxide semiconductor field effect transistor (MOSFET) and the amount of gate leakage current has increased due to a reduction in the thickness of a gate insulating film. Therefore, the following techniques have been examined: a technique that uses a metal gate electrode to avoid the depletion of the electrode; and a technique that forms a gate insulating film made of a high-dielectric-constant material to increase the physical thickness of the film, thereby reducing a gate leakage current.
As an example of a MOSFET including a metal gate electrode and a high-dielectric-constant insulating film, a structure has been proposed in which an interface insulating film made of, for example, SiO2, a high-dielectric-constant insulating film, a metal gate electrode, and a polysilicon gate electrode are laminated on a semiconductor substrate. In the MOSFET having the above-mentioned structure, it is important to adjust a threshold voltage. In an NMOSFET, a very small amount of metal material different from that forming a metal gate electrode locally exists between an interface insulating film and a high-dielectric-constant insulating film to control a work function. In this way, it is possible to reduce the threshold voltage.
Japanese Unexamined patent publication NO. 2008-53283 discloses a technique in which a hafnium silicate insulating film is formed on an underlying insulating film made of, for example, SiO2, and a metal material is patterned by photolithography and a metal etching process to form a metal tantalum film only on the hafnium silicate insulating film of an NMOSFET.
PCT Publication No. WO2004/008544 discloses a technique that thermally diffuses a metal element, such as La, from the surface of a SiO2 gate insulating film in a MOSFET including a gate insulating film made of SiO2. In this way, a gate insulating film structure is manufactured in which the concentration of the metal element is the highest in the surface of the SiO2 gate insulating film, is reduced as the depth of the gate insulating film is increased, and is approximately zero at a predetermined depth from the surface of the gate insulating film.
Next, an example of a method of manufacturing a semiconductor device that patterns a metal material using photolithography and a metal etching process such that La locally exists only between a silicon oxide film 116, which is an interface insulating film, of an NMOSFET and a HfO2 film 118, which is a high-dielectric-constant insulating film, will be described with reference to FIGS. 8A, 8B, and 8C and FIGS. 9A, 9B, and 9C.
First, as shown in FIG. 8A, the silicon oxide film 116 and the HfO2 film 118 are formed on a semiconductor substrate 110. Then, a La film 120 is deposited on the entire surface of the HfO2 film 118 by, for example, a sputtering method. A P well 112, which is an NMOSFET forming region, an N well 113, which is a PMOSFET forming region, and an element isolation insulating film 111 have already been formed on the semiconductor substrate 110.
Then, as shown in FIG. 8B, a resist mask 122 is formed so as to cover only the La film 120 formed in the P well 112. Then, wet etching is performed on the La film 120 exposed from the PMOSFET forming region with a dilute hydrochloric acid, using the resist mask 122 as a mask (FIG. 8C), and the resist mask 122 is removed by H2/N2 plasma ashing. In this way, as shown in FIG. 9A, the La film 120 is formed only in the NMOSFET forming region, and the HfO2 film 118 is exposed from the PMOSFET forming region.
Then, as shown in FIG. 9B, a metal gate electrode 124 and a polysilicon electrode 126 are formed. As shown in FIG. 9C, the metal gate electrode 124 and the polysilicon electrode 126 are processed into a gate electrode. Then, impurities are implanted to form source and drain regions, a side wall is formed, and a heat treatment is performed to form an NMOSFET and a PMOSFET (not shown). In the NMOSFET, a heat treatment is performed to diffuse La into the HfO2 film 118 and into the interface between the HfO2 film 118 and the silicon oxide film 116.
In the method of manufacturing the semiconductor device, after the La film 120 is formed on the HfO2 film 118 provided in the PMOSFET forming region once, the La film 120 disposed in the PMOSFET forming region is removed by wet etching. In this case, as shown in FIG. 8C, the La film 120 on the HfO2 film 118 that is formed in the PMOSFET forming region is not sufficiently removed by wet etching, but about 1E14 atoms/cm2 of La 121 remains on the surface of the HfO2 film 118. When a metal gate electrode 124 and a polysilicon electrode 126 are formed on the La 121, the threshold voltage of the PMOSFET is increased.